The present invention relates to power semiconductor device structures for high-voltage and/or high-power operating conditions.
Emitter switching is a circuit configuration in which a low-voltage power transistor (typically an MOS transistor) cuts off the emitter current of a high-voltage power transistor (typically a bipolar transistor) in order to switch it off. This configuration offers the following advantages:
it helps protect the bipolar transistor against reverse secondary breakdown (ESB); PA0 it combines the current and voltage carrying capacity of a piloted transistor and the high speed of a low-voltage transistor; PA0 it enables the system to be piloted directly with linear logic circuits, through the MOS gate.
U.S. Pat. Nos. 5,118,635 and 5,065,213 describe a pioneering improvement in switched-emitter device structures. In the primary embodiment described in these patents, a power bipolar transistor is overlaid with a power MOS (VDMOS) device. The VDMOS device is a vertical-current-flow device which is easily switched by an insulate gate at its surface. The drain of the VDMOS device is a buried layer which ALSO functions as the emitter of a power bipolar device. Thus the on or off state of the VDMOS changes the potential of the bipolar device's emitter (hence the name of the device). The base of the bipolar device is another buried layer (surrounding and deeper than the emitter layer), which is held at constant potential. When the VDMOS is turned on, its conduction pulls up the drain/emitter diffusion. This forward biases the base/emitter junction to turn on the bipolar. Once the bipolar is turned on it provides a lower on-resistance per unit area than would a MOS transistor of the same breakdown voltage (due to bipolar conduction and associated regeneration gain). Thus this structure provides a uniquely advantageous improvement in the tradeoff between on-resistance Ron and breakdown voltage Vmax.
The present application provides a combined structure which includes a high-voltage bipolar power transistor, and a low-voltage vertical-current-flow MOS power transistor structure which has its channel formed in a recess, combined in an emitter switching configuration.
In the disclosed embodiments the vertical MOS device is not necessarily a VDMOS device, but instead is built in a top p- epi layer, and is laterally dielectrically isolated from the sinker diffusions which make contact to the base of the bipolar transistor. (The top p- epi layer is not readily adaptable to VDMOS devices.)
In a first sample embodiment, the MOS transistor is a VMOS device.
In a second sample embodiment, the MOS transistor is a trench transistor.